“Dual-damascene construction,” “dielectric constants,” “channel length,” “gate counts,” “cell densities.” This is the peculiar language of microscopic wizardry. It is spoken in IBM’s micro-electronics labs by people with arguably peculiar fixations—such as storing 100,000 pages of data in the space the size of a dime, placing 12,000 wires side by side on the head of a pin, or jamming 200 million transistors onto a single chip.

No less peculiar is the distinct and, one could argue, mutually exclusive ambition of conventional computer chip design that calls for squeezing more and more functionality and speed from an ever-shrinking surface.

Happily, IBM research facilities are filled with people who fervently embrace this paradox—modern Michelangelos who sculpt in silicon instead of stone—constructing exceedingly complex functional art best viewed under scanning electron microscopes. Their perpetually shrinking world interacts with ours in the profusion of intelligent gadgetry that supports our work, travel, communication, and play. Invisible, both literally and figuratively, are the obstacles encountered in the process of etching big demands onto tiny slivers of silicon.

One of those demands is, of course, faster execution, and IBM microelectronics boasts of several breakthroughs that promise to increase chip performance 30 to 40 percent. This new generation of complementary metal oxide semiconductors, known as CMOS 7S, will likely appear in selected AS/400s by the end of this year. They are the product of a decade of intense research and break some formidable barriers to submicron miniaturization.

One of the primary benefits to miniaturization is, of course, speed. Smaller transistors switch faster; the more diminutive the chip surface, the shorter the length a signal has to travel, thus improving clock speeds. At least that was the traditional method of improving chip performance, and, for a long time, it worked reliably.

But, as things got smaller, the rules changed. Below the 0.5 micron level (a micron is measured as one-millionth of a meter), critical materials were stressed to the limit of

their performance. Paradoxically, with the increase in transistor densities, merely shrinking the design no longer guaranteed that the signal path length would be reduced. Yes, the chip itself was smaller, but now there was so much more stuff on it that if you had to push the signal from one end of the chip to the other, it might take longer to run the gauntlet. In that scenario, an increase in pure transistor speed yielded diminishing clock speeds.

Making it smaller no longer made it faster.

Perhaps the biggest challenge for designers approaching Lilliputian geometries of
0.15 microns was finding a workable substitute for aluminum traces—the wires that interconnect transistors. Aluminum has been the standard for 30 years, primarily because it behaves itself in a silicon environment. Ideally, designers would have preferred to use copper, a more conductive metal, and, therefore, a faster signal transmitter than aluminum. But copper, when it comes in contact with silicon, goes berserk, scattering atoms like pollen and ultimately corrupting the chip’s functions. For years, numerous chip manufacturers toyed with the copper puzzle, searching for a way to make copper and silicon coexist, and finally IBM solved it.

“To use copper in the chip fabrication process,” explained Bill O’Leary, manager of media relations at IBM microelectronics, “three problems had to be solved in such a way that would not require major retooling.” The ability to leverage existing fabrication technologies was key to keeping development costs viable. The price tag for building a modern fab, as chip manufacturing plants are known, is on the order of $2 billion—much of that capital invested in highly specialized machines that do the work human hands and eyes cannot. The equipment is of such cost and complexity that major modifications to the manufacturing process are prohibitive.

“The first problem,” O’Leary explained, “was how to put the wire on the silicon.” With aluminum, a technique called chemical vapor deposition, which evaporates metal directly onto the silicon surface, was used. But that method didn’t work with copper. Instead, IBM engineers developed a proprietary chemical process that O’Leary colorfully described as “quasi-electroplating.”

Second, once you get the copper down, how can you keep it from shedding atoms? When distances are measured in fractions of microns (less than 1/500 the width of a human hair), contamination, oxidation, and signal integrity are problematic. IBM’s solution was to develop a barrier layer, a coating that prevented the copper from diffusing into the silicon. On a submicron level, however, coated wires are like sumo wrestlers flying coach class: They take up too much space. Whatever the barrier solution, therefore, it had to be ultra-thin.

“So, what is the solution?” I asked. Since many manufacturers would give their eyeteeth for the answer to that question, O’Leary politely declined to be more specific.

The third challenge was layering or, more precisely, planing and polishing the surface of a chip so that other layers could be added. Layering is a process developed to gain additional space on a chip by stratifying its circuitry. Prior to adding a new layer, however, the preceding layer must be sealed and polished, but the process used with aluminum will smear copper, rendering it useless. IBM developed a chemical-mechanical planarizing process that allows six layers to be stacked on each chip, and O’Leary says more layers can be added as needed.

In combination, these changes were so elegantly designed, noted O’Leary, that they actually reduced the number of steps in the manufacturing process.

But now, imagine, on the one hand, having a computer-generated design that allows up to 12 million gates on a single chip, a design that can pack between 150 million

and 200 million transistors on a sliver. On the other hand, you have a blank silicon wafer. How do you transfer the design to the chip surface?

With light. Light is passed through a series of lenses and mirrors, through a mask of the image to be printed, and is projected onto the silicon. The process is called optical lithography, but it is only able to shrink design images down to about the 0.20 micron level. Below that, the light blurs and the image is inexact.

IBM developed a lithography process using X-rays. The shorter light wavelength in the X-ray spectrum allows a crisper image to be projected. IBM development teams have already demonstrated the capability of X-ray lithography to build chips with circuitry features of 0.15 microns and below, and the company boasts having the only commercial X-ray chip-making operation in the United States. The technologies and manufacturing

techniques described above will be used to develop, among other things, 1 gigabit DRAMs—memory chips with the capacity to store a billion bits of information.

Now that IBM has tamed copper-based microchip technology and created a manufacturing process that is both reliable and repeatable, it hopes to pick up a sizeable share of the exploding application-specific integrated circuits (ASIC) market predicted to reach $40 billion by the year 2001. ASICs are used in a wide range of commercial applications—from computers and sophisticated communications devices to consumer electronics.

ASIC chips, O’Leary explained, are designed to perform specialized functions such as manipulating 3D graphics or controlling digital cameras. The idea is that many commercial functions are predictable and repeatable, so there’s no need to reinvent the wheel each time a new chip is constructed. ASICs combine reusable existing pieces of design logic, called cores, with custom logic. As the complexity of chip design increases, and customers demand faster delivery, using any of the more than 50 proven cores in IBM’s core library can reduce fabrication and testing time for electronics manufacturers.

To accommodate the added demands of high-speed communications, IBM researchers solved another molecular riddle: how to combine two incompatible elements, silicon and germanium (a brittle crystalline metalloid substance). Experiments showed that taking out about 10 percent of the silicon atoms and replacing them with germanium produced faster-functioning transistors.

The catch is that germanium atoms are bigger than silicon atoms, but IBM researchers found a way to make the device stable, and the results are silicon germanium chips that have the ability to operate at speeds greater than 100 GHz, roughly 500 times faster than the microprocessors found in today’s advanced desktop PCs. Such chips are particularly useful in communications devices operating at high frequencies.

The future for the AS/400, and indeed for global communications and consumer electronics, seems boundless. According to Vijay Lund, director of PowerPC development, copper chips that pack more than 30 times the circuitry and function of today’s Intel Pentium chips will appear first in the AS/400 and RS/6000. But even before the first customers take delivery, we can be certain that there are already new miracles being etched in silicon that will one day make today’s breakthroughs seem pedestrian.

Certainly, IBM seems to be cranking out new generations of chips faster than a patient and gracious Bill O’Leary can explain them to me. Smaller, faster, more functional in endless refrain: It’s enough to make the neurotransmitters in my cerebral cortex spin.

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