Last month, IBM used the Hot Chips microprocessor conference held at Stanford University to publicly discuss details about its next-generation POWER5 processor for the first time. Those details reveal much about the performance that customers can expect from the new iSeries servers that IBM should unveil in the spring of 2004.
As you know from articles that I have previously published, IBM intends to announce a new lineup of iSeries servers next year that utilize up to 64 POWER5 processors. When IBM briefed me about POWER5 several months ago, it required me to sign a nondisclosure agreement that remained in effect until the Hot Chips conference. Now that the conference is over, I can share much of what I know with you about the processor's design and its future on the iSeries.
The POWER5 chip bears several similarities to the current POWER4+ processors that run on the latest pSeries servers. Like POWER4+, the POWER5 processors will initially utilize a 0.13-micron lithography process; in 2005, the POWER5+ will shrink down to a 0.09-micron process. The POWER5 also incorporates the dual-core design (i.e., two CPUs per chip) found on both POWER4 and POWER4+ as well as an on-chip L2 cache that is shared between processor cores.
Beyond these similarities, however, POWER5 will be a much faster and smarter chip than its predecessors. Here are the key enhancements that IBM is building into the processor.
- Simultaneous Multithreading (SMT)--With POWER5, each processor core will be able to execute two threads concurrently. This enhancement is similar to the HyperThreading feature found on Intel's latest Xeon processors. For some applications--particularly those that are object-oriented and highly granular--SMT will boost overall performance by 40% or more. Moreover, SMT will not require any application recoding to take advantage of the feature. However, many applications written in older procedural languages will realize little to no performance gain from SMT.
- More on-board cache and controllers--As part of the processor design, IBM is putting more components on the same chip as the CPU cores. This reduces data path lengths and allows for faster cycle times. Specifically, IBM is bringing the main memory controller and L3 cache into the POWER5 processor chip. It is also increasing the size of the L2 cache from 1.5 MB to around 2 MB. This will allow the initial batch of POWER5 processors to run at cycle times of 2 GHz or slightly higher. However, IBM will likely offer POWER5 servers running at two or three different cycle times, including at least one cycle time under 2 GHz.
- Dynamic power management--Because it will have more on-board components and transistors than previous designs, POWER5 will be about 24% larger than POWER4+. Under normal circumstances, this would increase power consumption and heat, two of the greatest enemies of processor design. To avoid both of these problems, IBM has added logic to the chip that enables it to shut off power to components that are not in use.
- Acceleration technologies--For POWER5, IBM will make a handful of improvements to boost both floating point and database processing. I cannot offer more information about those improvements at this time, but I will do so as soon as I can.
Clearly, POWER5 will represent an enormous performance boost for the iSeries. According to sources within IBM, the vendor will probably announce POWER5 versions of the iSeries during the opening weeks of spring in 2004. The first POWER5 models to ship will likely be smaller servers with up to eight processors; models with more processors will probably ship one to two months later. The largest models will feature...
- 64 processors
- Either 512 GB or 1 TB of memory
- Support for up to 256 logical partitions running OS/400, Linux, and AIX
- A performance rating of approximately 150,000 CPW (roughly four times the performance of the current 32-way iSeries 890)
As for the pricing of the new servers, IBM is disclosing nothing publicly. Obviously, customers will enjoy a significant improvement in their raw costs per CPW. However, the big question will be whether IBM reduces prices for memory, disk storage, and other items that make up the lion's share of server costs.
I can tell you that there are discussions taking place within IBM about those prices and that those discussions are focusing on whether to use the POWER5 announcement to "equalize" prices for iSeries and pSeries server components. Such a move would make sense given the fact that, with POWER5, the iSeries and pSeries will be able to run each other's operating systems. If IBM does use POWER5 to introduce component price parity, it could dramatically reduce prices for iSeries hardware features that are shared with the pSeries. However, IBM's pricing deliberations are far from over, so nothing is set in stone yet. As details emerge in the coming months, I'll be sure to share them with you, so stay tuned.
Lee Kroon is a Senior Industry Analyst for Andrews Consulting Group, a firm that helps mid-sized companies manage business transformation through technology. You can reach him at
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